1. Field of the Invention
The invention relates to a semiconductor process. More particularly, the invention relates to a method for fabricating capacitors.
2. Description of the Related Art
The capacitor area of a DRAM capacitor is more critical at the 64 Mb level and beyond, as the design rule of the DRAM is tighter. Because a crown-shape capacitor has a large capacitor area, it is preferably used in a DRAM capacitor to increase the capacitance. However, fabrication of the crown-shape capacitor is very complex. Therefore, a simple method is needed to fabricate capacitors with a large capacitor area. cl SUMMARY OF THE INVENTION
In one aspect, the present invention provides a method for fabricating capacitors suitable for use in a dielectric layer having a first and a second opening. The first and the second openings are filled with a polysilicon layer that covers the dielectric layer. An oxide pattern having sidewalls is formed over the polysilicon layer. The oxide pattern exposes a first region, a second region and a third region of the polysilicon layer. The third region is located between the first and the second regions and aligned over a position between the first and second openings. On the sidewalls of the oxide pattern, spacers are formed to reduce areas of the first, the second, and the third regions. The spacers and the oxide pattern thus result in a first, a second, and a third windows exposing portions of the polysilicon layer, wherein the first and the second windows are both narrower than the third window positioned between them. The polysilicon layer is etched using the spacers and the oxide pattern as an etching mask until forming a trench that exposes the dielectric layer between the first and the second openings. A dielectric layer is formed over the polysilicon layer. A conductive layer is formed over the dielectric layer.
The spacers are formed to reduce the width of the windows. According to a micro-loading effect, the narrow windows facilitate the increase of the area of capacitors.
In another aspect, the present invention provides a method of fabricating storage nodes. A dielectric layer having a first opening and a second opening is provided. The first and the second openings are filled with a polysilicon layer that covers the dielectric layer. An oxide pattern having sidewalls is formed over the polysilicon layer. The oxide pattern exposes at least a first region, a second region and a third region of the polysilicon layer. The third region is located between the first and the second regions and aligned over a position between the first and second openings. On the sidewalls of the oxide pattern, spacers are formed to reduce areas of the first, the second, and the third regions. The spacers and the oxide pattern have a first, a second, and a third windows exposing portions of the polysilicon layer, wherein the first and the second windows are both sufficiently narrower to cause an etching rate of the polysilicon layer beneath the first and the second windows slower than that beneath the third window. The polysilicon layer is etched using the spacer and the oxide pattern as an etching mask until forming a trench to expose the dielectric layer between the first and the second openings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.